Combinational building blocks#

A few types of logic circuit are often used as building blocks in larger design:

Decoder (binary to one-hot)#

One-Hot representation#

• Represent a set of $N$ elements with $N$ bits
• Exactly one bit is set
• Example – to encode numbers 0-7

n-to-m decoder#

• $n$ input variables; up to $2^n$ output lines( $m\le 2^n$ )
• binary to one-hot decoder

This is the description of decoder by Verilog:

// a - binary input (n bits wide)
// b - one hot output (m bits wide)
module Dec(a, b);
    parameter n = 2;
    parameter m = 4;
    input [n - 1:0] a;
    output [m - 1:0] b;
    wire [m - 1:0] b = 1 << a;
endmodule

With parameter in a module (Parameterized Module), we can decide those parameters while instantiation.

Dec dec2to4 (a, b); // Default parameters

Dec # (3, 8) dec3to8 (a, b); // Overriding the parameters

Dec # (.n(4), .m(10)) dec4to10 (a, b); // An other method to overriding

This is the circuit of a 3 to 8 decoder:

Decoder with Enable input#

If the Enable is $0$, output $000...0$, if the Enable is $1$, output the normal output.

Decoder Tree#

It is a 4-to-16 decoder made by 2-to-4 decoder.

Utility#

Info:

Each output of a decoder is a minterm, so we can use a decoder and a external OR gate to implement any Boolean function.

Example 1#

Implement a Prime Number Detector for 0 to 8 with decoder.

module Primed(in, isprime);
    input [2:0] in;
    output isprime;
    wire [7:0] b;
    // compute the output as the OR of
    // the required minterms
    wire isprime = b[1] | b[2] | b[3] | b[5] | b[7];
    // instantiate a 3->8 decoder
    Dec #(.n(3), .m(8)) d(.a(in), .b(b));
endmodule

Example 2#

Implement a full adder with decoder. Remind that $z = C_{in}$.

Encoder (one-hot to binary)#

n-to-m encoder#

• An encoder provides the inverse function of a decoder
• Encoder converts an n-bit one-hot input signal to an m-bit binary-encoded output signal

By observing the truth, we can get the Boolean function:

Priority Encoder#

• Allows multiple input lines to be asserted
• Higher-numbered input line has higher priority
• A priority encoder examines the input bits of an n-bit word and produces an output that indicates the position of the highest priority logic 1 bit.

4-to-2 priority encoder#

By Kmap, we can get the logic expression and draw the circuit:

Multiplexer (select one of N)#

• A data selector
• $2^n$ data input lines, $n$ selection lines and one output line
• $b = a[i]$ if $sb = i$

2-to-1 multiplexer#

We can easily draw the circuit:

4-to-1 multiplexer#

We can write this multiplexer with verilog:

module Mux4to1(a3, a2, a1, a0, sb, b);
    input a0, a1, a2, a3; // inputs
    input [1:0] sb; // binary select
    output b;
    reg b;
    always @(*) begin
        case(sb)
            2’b00: b = a0;
            2’b01: b = a1;
            2’b10: b = a2;
            2’b11: b = a3;
            default: b = x;
        endcase
    end
endmodule

Mux tree#

Reuse the multiplexer to construct a mux tree:

Utility#

Info:

Any function of $n$ variables can be implemented with a single MUX with $n-1$ selection inputs.

Example 1#

Implement the following function with MUX:

Suppose we use X and Y as the selection inputs $S_1$ and $S_0$, respectively, then:

Example 2#

Implement the following function with MUX:

Using $A$, $B$, $C$ as $S_2$, $S_1$, $S_0$ respectively.

Tri-state Buffer#

• A type of buffer
• Output state : $0$, $1$, or $Z$ (high-impedance).

Mux implemented by Tri-state Buffer#

	2x1 MUX	4x1 MUX
Implementation

tags: Logic Design EECS1010#