Basic elements in Verilog#

Data type#

Value#

Number#

We represent numbers in verilog like this: <len>'<b, o, d, h><value>

• <len> : Use decimal number to represent how many bits.
• <b, o, d, h> : Represent binary, octal, decimal, hexadecimal.
• <value> : We can use _ to seperate bits.
• RMK : Use b need to type out all bits. For example:

a = 32'd0;
b = 6'b000101;
c = 8'h0A;
d = 8'b0101_1010;

parameter#

• It is a const that is unchangeable

Example :

parameter width = 32;
reg [width-1:0]a; //a_32bit_reg

wire#

• No memory ability.
• Default value is z.
• It is not allowed to connect two wire.

reg#

• Has memory ability.
• Default value is x.
• We will use this in always since we need to record last Example :

reg [7:0]a; //a_8bit_reg
reg [3:0]b[31:0]; // 32 * (4_bit_reg)

input#

• Inside a module : wire
• Outside a module : wire, reg

output#

• Inside a module : wire, reg
• Outside a module : wire

Gate Level#

There are some default logic gate module build in Verilog that you can use it as instantiation. <gate_name> <variable_name> (output, in1, in2);

• <gate_name> : not, or, and, xor …

Example : Half adder

//Half adder
module Half_adder(a, b, carry, sum);
    input a;
    input b;
    output carry;
    output sum;
    and andl(carry, a, b); //AND gate carry = a and b
    xor xor1(sum, a, b); //XOR gate sum = a xor b
endmodule

Dataflow Level#

Assign#

Behavoir Level#

Always block#

• Use begin and end to represent { and } for multiple lines.
• Assign value : <reg> = <wire, reg>.
• For positive edge trigger use posedge, otherwise use negedge, for any change to trigger, just type the signal.
• For multiple trigger condition, use or or ..
• For the situation that you want to run always no matter what happens, use always@(*) .

always@(posedge clkSys or negedge rst_n)begin
    ...
    ...
end

always@(b)
  ...

wire in_1;
reg out_1;

always@(*)
  out_1 = in_1;

If - else#

if(...)begin
  if()begin
    ....
  end
  else begin
    ....
  end
end
else if(...)begin
  ....
end
else begin
  ....
end

Case#

case(...)
  item_1:begin
    ....
  end
  item_2:begin
    ....
  end
  item_3:begin
    ....
  end
  item_4:begin
    ....
  end
  default:begin
    ....
  end
endcase

for-loop#

We usually use for in TestBench to do

tags: Logic Design EECS1010#