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Examples#

Verilog Description of Majority Function#

Majority Function is the Boolean function that evaluates to false when half or more arguments are false and true otherwise. Here is its block diagram: Here is its logic function:

f(a,b,c)=(a∧b)∨(a∧c)∨(b∧c)f(a,b,c)=(a \land b) \lor (a \land c) \lor (b \land c)

Majority.v#

module Majority(a, b, c, out);
    input a, b, c;
    output out;
    wire out;
    assign out = (a & b) | (a & c) | (b & c);
endmodule
verilog

Test.v#

module test;
    reg [2:0] count; // input - three bit counter
    wire out; // output of majority
    // instantiate the block
    Majority m(count[0], count[1], count[2], out);
    // generate all eight input patterns
    initial begin
        count = 3'b000;
        repeat (8) begin
        #100
        $display(“in = %b, out = %b”, count, out);
        count = count + 3'b001;
        end
    end
endmodule
verilog
tags: Logic Design EECS1010#