Torrid Fish

Back

Introduction to Verilog#

Basic concept of Verilog#

A Hardware Description Language (HDL)#

Used as design description for Synthesis and simulation

  • Synthesis Implement hardware with a network of logic gates/cells in ASIC or FPGA
  • Simulation See what your hardware will do before you build it

Basic unit is a module#

Modules have:

  • Module declaration
  • Input and output declarations
  • Internal signal declarations
  • Logic definition

There are three Logic definitions:

  1. Assign statements
  2. Case statements
  3. Submodule instantiation

Descript method#

There are four level to descript: (from high to low)

  • Behavioral level Only care about the ability of a circuit, the highest level.
  • Dataflow level We need to exactly deal with the signal with assign.
  • Gate level Composed with logic gates.
  • Switch level Comopsed with transistors.

Brief introduce#

A verilog module should look like this:

Verilog for Thermostat#

The / sign on a line shows that there are multiple inputs. For exaple, there are 3 inputs in A. Here is the code:

module Thermostat(presetTemp, currentTemp, fanOn);
    input [2:0] presetTemp, currentTemp ; 
    output fanOn; 
    wire fanOn ;
    assign fanOn = (currentTemp > presetTemp);
endmodule
verilog

There are multiple part of the code:

Module declaration#

We use this form to declare a module

module ...
    ...
endmodule
verilog

I/O list#

We put all the input and output in (), usually we put input at the front, and output at the end.

... (presetTemp, currentTemp, fanOn);
    ...
verilog

Declare I/O#

In the module, we need to declare what is the input and the output.

    input [2:0] presetTemp, currentTemp ; 
    output fanOn; //true when current > preset
verilog

The [2:0] is similar to python, it means it is a 3-bit wide signals, from left to right is [2],[1],[0][2], [1], [0].

Wire ( Signal )#

A wire is a signal set with an assign statement or connected to a module(Instantiation). Signal is not variable

    wire fanOn;
verilog

Assign#

An assign statement defines a signal with an equation

    assign fanOn = (currentTemp > presetTemp);
verilog

We will introduce more details in next chapter.

tags: Logic Design EECS1010#